Semiconductor memory devices such as dynamic random access memory (DRAM) devices are widely used in computers and other electronic devices. As the speed of such electronic devices increases, it is important that the speed of accessing data stored in the memory devices also increases or at least does not decrease as the density of the memory devices increases so that the electronic devices do not have to wait for data. Memory access speeds continue to increase as electronic device require greater amounts of data at increased delivery rates. Access speeds to DRAM devices are approaching 250 MHz and above. However, access speed may be limited by timing of memory access with other functions in the electronic device. The windows of time during which the memory is accessed decrease as the access speed increases. As a result, the length of time during which the memory device has to access the data stored therein (access window) has been reduced from the order of nanoseconds to picoseconds.
An enhancement of DRAM circuitry is the addition of isolation gates between the digit lines and a sense amplifier. Such isolation gates resistively separate the sense amplifier from the digit line capacitances. As a result, the sense amplifier latches data more quickly. The benefit of isolation gates is more significant for higher density DRAMs, which have longer digit lines, and thus higher digit line capacitances.
The isolation gates are controlled by a control signal which must be accurately timed in relation to other DRAM signals, such as the signal that activates the sense amplifier. There is a continuing need to supply DRAMs with greater memory capacity. As a result, the length of isolation gate control signal lines have increased. Accordingly, isolation signals experience an RC delay as the signals travel through the signal lines. If the timing of the control signal and other memory device signals are inaccurately timed, the sense amplifier may not operate as desired and errors will occur in reading the data from the memory device. Therefore, there is a need for a method to reduce timing inaccuracy and improve access speeds of DRAMS.